1. Field of the Invention
The present invention relates to a semiconductor memory device and its control method, and for example, to a semiconductor memory device provided with a correction circuit for correcting errors in information nonvolatilely stored in a semiconductor memory, and a method of controlling the device.
2. Description of the Related Art
Depending upon the type of nonvolatile memory device, the state of the physical amount of a memory corresponding to the amount of data stored therein varies with lapse of time. When a preset time elapses, data may be lost. Various memory devices have this property. For instance, a nonvolatile semiconductor memory device using, as memory cells, transistors having a so-called laminated gate structure is included in such memory devices.
The laminated gate structure comprises a tunnel insulation film, floating gate electrode, inter-gate insulation film and control gate electrode. To store information in a memory cell, electrons are injected from the substrate side into the floating gate electrode via the tunnel insulation film. The electric charge accumulated in the floating gate electrode serves as information. Since the electric charge accumulated in the floating gate electrode leaks into the substrate through the tunnel insulation film with lapse of time, with the result that the information stored in the memory cell will be lost with lapse of time (an error will occur in information).
If the time elapsing from the storage of information is short, the possibility of occurrence of errors in information is small. In contrast, if the time elapsing from the storage of information is long, the possibility of occurrence of errors in information is strong. Memory devices including such memory cells as the above may be provided with an error correction mechanism for correcting errors in information.
In general, a correction mechanism having a high error correction performance is necessary to correct errors that occur in information consisting of a plurality of bits because, for example, much time has elapsed. Correction mechanisms having a high error correction performance generally have a large circuitry scale, consume much power, and require much time for processing. However, to guarantee correct restoration of data even when much time elapses from the storage of the data, a correction mechanism having a high error correction performance is provided, and is always used regardless of the time elapsing from the storage of the data.
Thus, a correction mechanism of high error correction performance is used even to read information, from the storage of which only a short time elapses, namely, even to read information that does not contain so many errors. This is wasting of power.
Furthermore, in general, to enhance error correction performance, it is necessary to enlarge the information to be subjected to error correction. For instance, to enhance error correction performance, an error correcting code is generated in units of, for example, 4 k-byte data pieces, instead of 512-byte data pieces (each 4 k-byte data piece is formed by coupling a plurality of 512-byte data pieces). In this case, 4 k-byte data must be read even when 512-byte data is wanted to be read. This also increases the power consumption of the memory device.
The following document is regarded as a prior art reference related to the present invention:                JP-A 63-275225 (KOKAI)        
In the reference, a correction apparatus which has a high error correction capability is disclosed.